Semiconductor devices have, until recently, been based on planar technology, which imposes constraints in terms of miniaturization and choices of suitable materials, which will be further described below. The development of nanoscale technology and in particular the ability to produce nanowires has opened up a possibility of designing vertical semiconductor devices. For the purpose of this application a vertical semiconductor device should be interpreted as a device comprising of a substrate and at least one protruding structure, the protruding structure for example grown from the substrate. The protruding structure should be essential for the functionality of the device, for example forming the current-carrying channel. The length of the protruding structure is essentially longer than the diameter of the structure and the portion of the protruding structure not in contact with the substrate is substantially larger than the portion in contact with the substrate. Depending on the substrate surface, materials, and growth methods, different growth directions will be preferred, all such directions are meant to be included in the term vertical semiconductor device. In the following the protruding structures are exemplified with nanowires.
Semiconductor materials with narrow band gap, hereinafter referred to as III/V semiconductors, such as InAs and InSb, have high mobilities, high saturated carrier velocities and low contact resistances. This makes the materials good candidates for high-speed and low-power electronics, and over the recent years the interest in using these materials in a large variety of semiconductor devices has shown a significant increase. However, transistors made of these materials often suffer from poor current control, small current on/off ratios, strong thermal effects, and a large output conductance related to the narrow band gap. In addition, structures of III/V semiconductors should preferably, in order to be commercially interesting, be compatible with existing silicon based technology, for example be possible to fabricate on Si-substrates. This is, with conventional technology, difficult, due to the large lattice mismatch between Si and III/V semiconductor materials. These above mentioned effects limit the application areas of the III/V semiconductors devices and reduce the performance of analogue and digital applications.
Semiconductor materials with wide bandgap, hereinafter referred to as nitride semiconductors, such as GaN, InGaN, and AlGaN, are well suited for high voltage and high power applications. However, transistors made of these materials suffer from poor material quality due to high material mismatch between the nitrides semiconductors and the substrate they are fabricated from. Also, the high cost of substrates, as sapphire and SiC limit the potential application areas of nitride semiconductor devices.
In a typical planar Field Effect Transistor (FET) the source-drain current is confined to a planar layer of semiconductor material. This means that it is not possible to use heterostructures in the direction of the current path in the channel to improve the performance, as is done in vertical, for instance bipolar, transistors. It is also difficult to fabricate heterostructures with narrow bandgap materials: in III/V semiconductors due to the lack of suitable lattice matched materials and problems with Sb-based compounds, and for Ge, the large lattice mismatch to Si and SiC.
The growth of nanowires offers new possibilities in heterostructure design as radial strain relaxation allows a large range of new compositions to be fabricated. InP can, for example, be grown on InAs without defects as described by Samuelson et al., United States Patent Application US 2004/0075464 A1. It is also possible to use a substrate that is not lattice matched to the wires, which offers even more design flexibility and opens up a route to integrate III-V semiconductors on Si. Thus the above described problems can be mitigated by the use of devices of nanoscale dimensions. Hence, structures comprising nanowires are of special interest and will throughout the application be used as a non-limiting example. However, the method and device according to the present invention are, as appreciated by the skilled in the art, not limited to devices of nanoscale dimension, also larger structure could be envisaged.
Semiconductor nanowires is in this context defined as rod-shaped structures with a diameter less than 200 nm and a length up to several μm. The growth of semiconductor nanowires can be done in various ways, for example by Metal Organic Vapor Phase Epitaxy (MOVPE) using metal particles to assist the anisotropic growth, often referred to Vapor Liquid Solid growth (VLS), as in the above referred US application to Samuelson et al. Another proven method of growing epitaxial nanowire structures is by Selective Area Epitaxy (SAE).
Such protruding structures, as vertical devices, and nanowires set new demands on associated process steps and new process steps will have to be designed and invented in order to achieve precise device design. Especially, this is true for the process steps following after the vertical part of the device has been fabricated, post-growth processing in the nanowire device concept. Such process is the fabrication of layers where a precise surface area between the vertical part and the layer is of importance or where a high degree of flatness of the layer close to the nanowire is needed. The nanowire will act as a perturbation in the post-growth fabrication of any film, layer, electrode, or isolation that the nanowire shall protrude. This perturbation can be in form of shadowing of the film deposition or adhesion of the film onto the nanowire sidewalls.
A nanoscaled wrap gate field effect transistor comprises a nanowire as a current-carrying channel. In one end of the nanowire a source electrode, or source contact, is provided and in the opposite end a drain electrode/contact. Between the source electrode and drain electrode is a gate electrode/contact arranged. The gate contact encloses, or wraps, the nanowire and covers a portion, the gate portion of the nanowire. The gate portion defines a gate length. The gate length has great influence on the characteristics of the device. In many applications it is desirable to have short, typically below 100 nm, gate lengths. In order to achieve devices with predictable characteristics, the gate length should also be uniform and reproducible. Previous methods for example as described in “Vertical high mobility wrap-gated InAs nanowire transistor”, IEEE 2005, by Tomas Bryllert et al., gives a wrap gate that cover a major portion of the nanowire.